1. Field of the Invention
The present invention relates to a crystalline semiconductor 4 and, more particularly, to a silicon semiconductor in the form of a thin film and to a semiconductor device using such a silicon semiconductor. The invention also relates to a method of fabricating them.
2. Description of the Related Art
Thin-film transistors (TFTs) used as thin-film devices are roughly classified into two categories: planar type and staggered type. Of these TFTs, staggered TFTs having shapes as shown in FIGS. 5(A)-5(E) and 6(A)-6(C) are known. These staggered TFTs are hereinafter referred to as the edgeless type.
This edgeless type TFT has an active layer in the form of an island which has substantially the same shape as the gate electrode. As a result, any steps extending across the gate electrodes do not exist. They are named edgeless type because no steps are present.
The above-described absence of steps extending across the gate electrodes is quite advantageous to TFT characteristics and to production yield. It has been often observed that steps crossing the gate electrodes (substantially at right angles to them) cause the gate electrodes to break. In the edgeless type, it is unlikely that interconnection breakage is caused by such steps.
The semiconductor characteristics at the edges of the active layer in the form of islands are deteriorated by plasma damage or for other cause Therefore, there exists a leakage current flowing across the edges. When a gate electrode of interest is unselected (i.e., in the case of the N-channel type, zero voltage or negative voltage is applied to the gate electrode), a large amount of leakage current (also known as OFF current) flows. Hence, the integrated circuit characteristics are deteriorated.
Strictly, even the edgeless type should have edges in the active layer. The source and the drain are electrically interconnected through a very long detour running along the gate electrode. In the prior art structure, the source and drain are interconnected nearly with the shortest distance. Therefore, the edgeless type is more effective in reducing OFF current than the prior art type.
In the edgeless type, steps running parallel to the gate electrodes do exist. These steps are mainly attributable to steps in source or drain. Since the steps parallel to the gate electrodes are little related to breakage of the gate electrode or to the OFF current, the TFT characteristics are affected only a little by these parallel steps.
Heretofore, the edgeless type TFT has been fabricated by the process sequence illustrated in FIGS. 5(A)-5(E). FIGS. 6(A)-6(C) are top views of the edgeless TFT illustrated in FIGS. 5(A)-5(E). First, a pair of N- or P-type amorphous or crystalline semiconductor regions 53 is formed on a glass substrate 51 directly or via a buffer layer 52 consisting of an appropriate insulator. An amorphous or crystalline intrinsic (N- or P-type impurity is not intentionally implanted) semiconductor layer 54 is formed so as to cover the semiconductor regions 53. Since the semiconductor layer 54 is made from the same material as source/drain regions 53, the semiconductor layer 54 is preferably sufficient thinner than the source/drain regions 53 so that no overetching will take place later (FIGS. 5(A) and 6(A)).
Then, a dielectric film 55 and a conductive film 56 are formed (Fig. 5(B)). The conductive film 56, the dielectric film 55, and the semiconductor layer 54 are etched to form gate electrode/interconnects 62, 63, gate-insulating films 60, 61, and semiconductor layers 58, 59. Since only one photolithography step is carried out for etching, the gate electrode/interconnects, gate-insulating film, and semiconductor layer have substantially the same shape (FIGS. 5(C) and 6(C)).
Thereafter, an interlayer insulator 64 is deposited. Contact holes are formed in the insulator 64. Source/drain electrodes/interconnects 65, 66 are formed (FIG. 5(D)). The laminate TFT structure obtained in this way assumes the state shown in FIG. 5(E).
As can be seen from FIG. 5(E), the semiconductor layer has substantially the same shape as the gate electrode and interconnects. Therefore, if the gate electrode is long, the semiconductor layer is elongated proportionately. The semiconductor layer is isolated from the gate interconnects only by a thin film such as a gate-insulating film. Consequently, a very great parasitic capacitance exists for the gate electrode. The result is that the operation speed of the circuit decreases. Also, the amount of electric power consumed is increased. Especially, where the semiconductor layer is made from crystalline silicon, a channel is induced more easily than in the case of amorphous silicon and so this is a serious problem. In the case of a large-area circuit such as an active matrix circuit, the problem is so serious that it is impossible to drive the circuit actually.
Furthermore, device isolation poses problems. No problem takes place if one gate electrode is provided for each one TFT. However, if one gate interconnect is formed over two or more TFTs as shown in FIG. 6(C), then a problem occurs. In this structure, if the gate electrode is turned ON, a channel is formed in the whole semiconductor layer located under the gate electrode. This is described in further detail by referring to FIG. 7(A).
In FIGS. 7(A) and 7(B), gate electrodes of two TFTs of the construction shown in FIG. 6(C) are formed by one gate interconnect 76. When the gate interconnect 76 is turned ON, an ON signal is applied to the source 72 of the first TFT, and an OFF signal is applied to the source 73 of the second TFT. The output signal from the drain 74 of the first TFT and the output signal from the drain 75 of the second TFT are also shown in FIGS. 7(A) and 7(B).
Since the gate electrode/interconnect 76 is ON, a channel is created in a semiconductor layer 77. An electric current 78 flows from the source 72 of the first TFT to the drain 74. At the same time, however, an interference current 79 flows into the drain 75 of the second TFT, because the channel is formed over the whole surface of the semiconductor layer 77. This is represented by the equivalent circuit of FIGS. 8(A) and 8(B). In FIG. 8(A), the gate electrode is OFF. At this time, no channel is created and so no drain current is produced. Of course, no interference current is produced. In FIG. 8(B), the gate electrode is ON. At this time, a drain current is produced, and a channel creates a conductive path (indicated by the symbols of resistors) to the adjacent TFT.
The interference current 79 decreases as the spacing between the first and second TFTs increases because the channel has a finite resistance as shown in FIG. 8(B). In order to provide sufficient device isolation, however, the size of each device is increased greatly. For example, if the distance between the first source and the first drain is 10 .mu.m, then it is necessary to set the distance between the adjacent TFTs to greater than 1 mm in order to reduce the interference current by a factor of more than 100.
In order to circumvent this problem, it has been heretofore necessary that only one gate electrode/interconnect be provided for each one TFT. If it is necessary to drive the gate electrode/interconnect as one unit, the gate electrode must be connected via the top metallization layer. In this structure, however, the contact between adjacent metallization layers is increased. This reduces the production yield. In an active matrix circuit, it is necessary to use the top metallization layer as data lines. Therefore, additional conductive interconnects are needed. Alternatively, it is necessary to form those portions which are other than the portions crossing the data lines out of the same metallization layer as the data lines. In the former structure, however, the number of metallization layers is increased. This in turn increases the number of manufacturing steps. That is, the productivity decreases. In the latter structure, the contact between the adjacent metallization layers increases further, thus deteriorating the production yield. Indeed, none of these structures can be put into practical use.